A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS
In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamic voltage scaling (DVS) capability is important since significant active as well as leakage power savings...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| Online Access: | http://hdl.handle.net/1721.1/53553 https://orcid.org/0000-0002-5977-2748 |
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| author | Verma, Naveen Sinangil, Mahmut Ersin Chandrakasan, Anantha P. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Verma, Naveen Sinangil, Mahmut Ersin Chandrakasan, Anantha P. |
| author_sort | Verma, Naveen |
| collection | MIT |
| description | In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamic voltage scaling (DVS) capability is important since significant active as well as leakage power savings can be achieved by voltage scaling. However, optimizing circuit operation over a large voltage range is not trivial due to conflicting trade-offs of low-voltage (moderate and weak inversion) and high-voltage (strong inversion) transistor characteristics. Specifically, low-voltage operation requires various assist circuits for functionality which might severely impact high-voltage performance. Reconfigurable assist circuits provide the necessary adaptability for circuits to adjust themselves to the requirements of the voltage range that they are operating in. This paper presents a 64 kb reconfigurable SRAM fabricated in 65 nm low-power CMOS process operating from 250 mV to 1.2 V. This wide supply range was enabled by a combination of circuits optimized for both subthreshold and above-threshold regimes and by employing hardware reconfigurability. Three different write-assist schemes can be selectively enabled to provide write functionality down to very low voltage levels while preventing excessive power overhead. Two different sense-amplifiers are implemented to minimize sensing delay over a large voltage range. A prototype test chip is tested to be operational at 20 kHz with 250 mV supply and 200 MHz with 1.2 V supply. Over this range leakage power scales by more than 50 X and a minimum energy point is achieved at 0.4 V with less than 0.1 pJ/bit/access. |
| first_indexed | 2024-09-23T13:45:41Z |
| format | Article |
| id | mit-1721.1/53553 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T13:45:41Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/535532022-09-28T15:58:11Z A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS Verma, Naveen Sinangil, Mahmut Ersin Chandrakasan, Anantha P. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology. Microsystems Technology Laboratories Chandrakasan, Anantha P. Verma, Naveen Sinangil, Mahmut Ersin Chandrakasan, Anantha P. low-power SRAM design dynamic voltage scaling circuit reconfigurability cache memories In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamic voltage scaling (DVS) capability is important since significant active as well as leakage power savings can be achieved by voltage scaling. However, optimizing circuit operation over a large voltage range is not trivial due to conflicting trade-offs of low-voltage (moderate and weak inversion) and high-voltage (strong inversion) transistor characteristics. Specifically, low-voltage operation requires various assist circuits for functionality which might severely impact high-voltage performance. Reconfigurable assist circuits provide the necessary adaptability for circuits to adjust themselves to the requirements of the voltage range that they are operating in. This paper presents a 64 kb reconfigurable SRAM fabricated in 65 nm low-power CMOS process operating from 250 mV to 1.2 V. This wide supply range was enabled by a combination of circuits optimized for both subthreshold and above-threshold regimes and by employing hardware reconfigurability. Three different write-assist schemes can be selectively enabled to provide write functionality down to very low voltage levels while preventing excessive power overhead. Two different sense-amplifiers are implemented to minimize sensing delay over a large voltage range. A prototype test chip is tested to be operational at 20 kHz with 250 mV supply and 200 MHz with 1.2 V supply. Over this range leakage power scales by more than 50 X and a minimum energy point is achieved at 0.4 V with less than 0.1 pJ/bit/access. Defence Advanced Research Projects Agency 2010-04-07T20:16:43Z 2010-04-07T20:16:43Z 2009-11 Article http://purl.org/eprint/type/JournalArticle 0018-9200 INSPEC Accession Number: 10957790 http://hdl.handle.net/1721.1/53553 Sinangil, M.E., N. Verma, and A.P. Chandrakasan. “A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS.” Solid-State Circuits, IEEE Journal of 44.11 (2009): 3163-3173. © 2009 Institute of Electrical and Electronics Engineers. https://orcid.org/0000-0002-5977-2748 en_US http://dx.doi.org/10.1109/jssc.2009.2032493 IEEE Journal of Solid-State Circuits Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | low-power SRAM design dynamic voltage scaling circuit reconfigurability cache memories Verma, Naveen Sinangil, Mahmut Ersin Chandrakasan, Anantha P. A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS |
| title | A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS |
| title_full | A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS |
| title_fullStr | A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS |
| title_full_unstemmed | A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS |
| title_short | A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS |
| title_sort | reconfigurable 8t ultra dynamic voltage scalable u dvs sram in 65 nm cmos |
| topic | low-power SRAM design dynamic voltage scaling circuit reconfigurability cache memories |
| url | http://hdl.handle.net/1721.1/53553 https://orcid.org/0000-0002-5977-2748 |
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