Bounded Dataflow Networks and Latency-Insensitive Circuits

Bounded Dataflow Networks and Latency-Insensitive Circuits

We present a theory for modular refinement of Synchronous Sequential Circuits (SSMs) using Bounded Dataflow Networks (BDNs). We provide a procedure for implementing any SSM into an LI-BDN, a special class of BDNs with some good compositional properties. We show that the Latency-Insensitive property...

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Bibliographic Details
Main Authors: Vijayaraghavan, Muralidaran, Arvind, Arvind
Other Authors: Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers 2010
Online Access:http://hdl.handle.net/1721.1/58834
https://orcid.org/0000-0002-9737-2366
https://orcid.org/0000-0003-0599-0800

Internet

http://hdl.handle.net/1721.1/58834
https://orcid.org/0000-0002-9737-2366
https://orcid.org/0000-0003-0599-0800

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