Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stac...

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Bibliographic Details
Main Authors: Keast, Craig L., Chen, Chang-Lee, Chen, Chenson K., Yost, Donna-Ruth W., Knecht, Jeffrey M., Wyatt, Peter W., Burns, James A., Warner, Keith, Gouker, Pascale M., Healey, Paul D., Wheeler, Bruce D.
Other Authors: Lincoln Laboratory
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers 2010
Online Access:http://hdl.handle.net/1721.1/58963

Internet

http://hdl.handle.net/1721.1/58963

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