Wafer-scale 3D integration of silicon-on-insulator RF amplifiers
RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stac...
| Main Authors: | , , , , , , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers
2010
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| Online Access: | http://hdl.handle.net/1721.1/58963 |
| _version_ | 1826207205460803584 |
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| author | Keast, Craig L. Chen, Chang-Lee Chen, Chenson K. Yost, Donna-Ruth W. Knecht, Jeffrey M. Wyatt, Peter W. Burns, James A. Warner, Keith Gouker, Pascale M. Healey, Paul D. Wheeler, Bruce D. |
| author2 | Lincoln Laboratory |
| author_facet | Lincoln Laboratory Keast, Craig L. Chen, Chang-Lee Chen, Chenson K. Yost, Donna-Ruth W. Knecht, Jeffrey M. Wyatt, Peter W. Burns, James A. Warner, Keith Gouker, Pascale M. Healey, Paul D. Wheeler, Bruce D. |
| author_sort | Keast, Craig L. |
| collection | MIT |
| description | RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved. |
| first_indexed | 2024-09-23T13:45:42Z |
| format | Article |
| id | mit-1721.1/58963 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T13:45:42Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/589632022-10-01T16:59:06Z Wafer-scale 3D integration of silicon-on-insulator RF amplifiers Keast, Craig L. Chen, Chang-Lee Chen, Chenson K. Yost, Donna-Ruth W. Knecht, Jeffrey M. Wyatt, Peter W. Burns, James A. Warner, Keith Gouker, Pascale M. Healey, Paul D. Wheeler, Bruce D. Lincoln Laboratory Keast, Craig L. Keast, Craig L. Chen, Chang-Lee Chen, Chenson K. Yost, Donna-Ruth W. Knecht, Jeffrey M. Wyatt, Peter W. Burns, James A. Warner, Keith Gouker, Pascale M. Healey, Paul D. Wheeler, Bruce D. RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved. United States. Defense Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002) 2010-10-08T14:28:37Z 2010-10-08T14:28:37Z 2009-02 2009-01 Article http://purl.org/eprint/type/JournalArticle 978-1-4244-3940-9 http://hdl.handle.net/1721.1/58963 Chen, C.L. et al. “Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers.” Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on. 2009. 1-4. © 2009 Institute of Electrical and Electronics Engineers. INSPEC Accession Number: 10468225 en_US http://dx.doi.org/10.1109/SMIC.2009.4770536 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09 Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | Keast, Craig L. Chen, Chang-Lee Chen, Chenson K. Yost, Donna-Ruth W. Knecht, Jeffrey M. Wyatt, Peter W. Burns, James A. Warner, Keith Gouker, Pascale M. Healey, Paul D. Wheeler, Bruce D. Wafer-scale 3D integration of silicon-on-insulator RF amplifiers |
| title | Wafer-scale 3D integration of silicon-on-insulator RF amplifiers |
| title_full | Wafer-scale 3D integration of silicon-on-insulator RF amplifiers |
| title_fullStr | Wafer-scale 3D integration of silicon-on-insulator RF amplifiers |
| title_full_unstemmed | Wafer-scale 3D integration of silicon-on-insulator RF amplifiers |
| title_short | Wafer-scale 3D integration of silicon-on-insulator RF amplifiers |
| title_sort | wafer scale 3d integration of silicon on insulator rf amplifiers |
| url | http://hdl.handle.net/1721.1/58963 |
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