Performance analysis of ultra-scaled InAs HEMTs
The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental Id-Vgs data obtained from devices with gate lengths ranging from 30 to 50 nm, wh...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| Online Access: | http://hdl.handle.net/1721.1/59451 |
| _version_ | 1811071453127245824 |
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| author | del Alamo, Jesus A. Kim, Dae-Hyun Kharche, Neerav Luisier, Mathieu |
| author2 | Massachusetts Institute of Technology. Microsystems Technology Laboratories |
| author_facet | Massachusetts Institute of Technology. Microsystems Technology Laboratories del Alamo, Jesus A. Kim, Dae-Hyun Kharche, Neerav Luisier, Mathieu |
| author_sort | del Alamo, Jesus A. |
| collection | MIT |
| description | The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental Id-Vgs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yet-fabricated 20 nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage. |
| first_indexed | 2024-09-23T08:51:10Z |
| format | Article |
| id | mit-1721.1/59451 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T08:51:10Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/594512022-09-30T11:42:41Z Performance analysis of ultra-scaled InAs HEMTs del Alamo, Jesus A. Kim, Dae-Hyun Kharche, Neerav Luisier, Mathieu Massachusetts Institute of Technology. Microsystems Technology Laboratories del Alamo, Jesus A. del Alamo, Jesus A. Kim, Dae-Hyun The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental Id-Vgs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yet-fabricated 20 nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage. Semiconductor Research Corporation Semiconductor Research Corporation. Center for Materials, Structures and Devices Purdue University. Network for Computational Nanotechnology National Institute for Computational Sciences (U.S.) 2010-10-21T19:39:42Z 2010-10-21T19:39:42Z 2010-03 2009-12 Article http://purl.org/eprint/type/JournalArticle 978-1-4244-5640-6 978-1-4244-5639-0 INSPEC Accession Number: 11207514 http://hdl.handle.net/1721.1/59451 Kharche, N. et al. “Performance analysis of ultra-scaled InAs HEMTs.” Electron Devices Meeting (IEDM), 2009 IEEE International. 2009. 1-4. © 2010 Institute of Electrical and Electronics Engineers. en_US http://dx.doi.org/10.1109/IEDM.2009.5424315 2009 IEEE International Electron Devices Meeting (IEDM) Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | del Alamo, Jesus A. Kim, Dae-Hyun Kharche, Neerav Luisier, Mathieu Performance analysis of ultra-scaled InAs HEMTs |
| title | Performance analysis of ultra-scaled InAs HEMTs |
| title_full | Performance analysis of ultra-scaled InAs HEMTs |
| title_fullStr | Performance analysis of ultra-scaled InAs HEMTs |
| title_full_unstemmed | Performance analysis of ultra-scaled InAs HEMTs |
| title_short | Performance analysis of ultra-scaled InAs HEMTs |
| title_sort | performance analysis of ultra scaled inas hemts |
| url | http://hdl.handle.net/1721.1/59451 |
| work_keys_str_mv | AT delalamojesusa performanceanalysisofultrascaledinashemts AT kimdaehyun performanceanalysisofultrascaledinashemts AT kharcheneerav performanceanalysisofultrascaledinashemts AT luisiermathieu performanceanalysisofultrascaledinashemts |