Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
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| Формат: | Диссертация |
| Язык: | eng |
| Опубликовано: |
Massachusetts Institute of Technology
2010
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| Online-ссылка: | http://hdl.handle.net/1721.1/60185 |
| _version_ | 1826211445956673536 |
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| author | Shim, Keun Sup |
| author2 | Srinivas Devadas. |
| author_facet | Srinivas Devadas. Shim, Keun Sup |
| author_sort | Shim, Keun Sup |
| collection | MIT |
| description | Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010. |
| first_indexed | 2024-09-23T15:06:19Z |
| format | Thesis |
| id | mit-1721.1/60185 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T15:06:19Z |
| publishDate | 2010 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/601852019-04-12T13:46:24Z Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks Static and dynamic VC allocation for high performance, in-order communication in on-chip networks Shim, Keun Sup Srinivas Devadas. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010. Includes bibliographical references (p. 63-67). Most routers in on-chip interconnection networks (OCINs) have multiple virtual channels (VCs) to mitigate the effects of head-of-line blocking. Multiple VCs necessitate VC allocation schemes since packets or flows must compete for channels when there are more flows than virtual channels at a link. Conventional dynamic VC allocation, however, raises two critical issues. First, it still suffers from a fair amount of head-of-line blocking since all flows can be assigned to any VC within a link. Moreover, dynamic VC allocation compromises the guarantee of in-order delivery even when used with basic variants of dimension-ordered routing, requiring large reorder buffers at the destination core or, alternatively, expensive retransmission logic. In this thesis, we present two virtual channel allocation schemes to address these problems: Static Virtual Channel Allocation and Exclusive Dynamic Virtual Channel Allocation (EDVCA). Static VC allocation assigns channels to flows by precomputation when oblivious routing is used, and ensures deadlock freedom for arbitrary minimal routes when two or more VCs are available. EDVCA, on the other hand, is done at runtime, not requiring knowledge of traffic patterns or routes in advance. We demonstrate that both static VCA and EDVCA guarantee in-order packet delivery under single path routing, and furthermore, that they both outperform dynamic VC allocation (out-of-order) by effectively reducing head-of-line blocking. We also introduce a novel bandwidth-sensitive oblivious routing scheme (BSORM), which is deadlock-free through appropriate static VC allocation. Implementation for these schemes requires only minor, inexpensive changes to traditional oblivious dimension-ordered router architectures, more than offset by the removal of packet reorder buffers and logic. by Keun Sup Shim. S.M. 2010-12-06T17:35:07Z 2010-12-06T17:35:07Z 2010 2010 Thesis http://hdl.handle.net/1721.1/60185 681916763 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 67 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Shim, Keun Sup Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks |
| title | Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks |
| title_full | Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks |
| title_fullStr | Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks |
| title_full_unstemmed | Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks |
| title_short | Static and dynamic virtual channel allocation for high performance, in-order communication in on-chip networks |
| title_sort | static and dynamic virtual channel allocation for high performance in order communication in on chip networks |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/60185 |
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