Concurrent gate-level circuit simulation

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.

Bibliographic Details
Main Author:	Shelly, Jacinda R. (Jacinda Rene)
Other Authors:	Christopher J. Terman.
Format:	Thesis
Language:	eng
Published:	Massachusetts Institute of Technology 2011
Subjects:	Electrical Engineering and Computer Science.
Online Access:	http://hdl.handle.net/1721.1/61576

Internet

http://hdl.handle.net/1721.1/61576