Concurrent gate-level circuit simulation
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
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| Formato: | Tese |
| Idioma: | eng |
| Publicado em: |
Massachusetts Institute of Technology
2011
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| Acesso em linha: | http://hdl.handle.net/1721.1/61576 |
| Resumo: | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010. |
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