Bias-Stress Effect in Pentacene Organic Thin-Film Transistors
The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage [DELTA]V for a given current. An empirical equation describing [D...
| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers
2011
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| Online Access: | http://hdl.handle.net/1721.1/62183 https://orcid.org/0000-0003-3001-9223 https://orcid.org/0000-0002-0960-2580 https://orcid.org/0000-0002-0413-8774 |