Engineered Nanostructures for High Thermal Conductivity Substrates
In the DARPA Thermal Ground Plane (TGP) program[1],we are developing a new thermal technology that will enable a monumental thermal technological leap to an entirely new class of electronics, particularly electronics for use in high-tech military systems. The proposed TGP is a planar, thermal e...
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| 格式: | Article |
| 語言: | en_US |
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Nano Science and Technology Institute
2011
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| 在線閱讀: | http://hdl.handle.net/1721.1/64411 https://orcid.org/0000-0002-6846-152X |
| _version_ | 1826213158298058752 |
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| author | Varanasi, Kripa K. Chamarthy, Pramod Chauhan, Shakti de Bock, Peter Deng, Tao Kulkarni, Ambarish Mandrusiak, Gary Rush, Brian Russ, Boris Denault, Lauraine Weaver, Stanton Gerner, Frank M. Leland, Quinn Yerkes, Kirk |
| author2 | Massachusetts Institute of Technology. Department of Mechanical Engineering |
| author_facet | Massachusetts Institute of Technology. Department of Mechanical Engineering Varanasi, Kripa K. Chamarthy, Pramod Chauhan, Shakti de Bock, Peter Deng, Tao Kulkarni, Ambarish Mandrusiak, Gary Rush, Brian Russ, Boris Denault, Lauraine Weaver, Stanton Gerner, Frank M. Leland, Quinn Yerkes, Kirk |
| author_sort | Varanasi, Kripa K. |
| collection | MIT |
| description | In the DARPA Thermal Ground Plane (TGP)
program[1],we are developing a new thermal technology
that will enable a monumental thermal technological leap
to an entirely new class of electronics, particularly
electronics for use in high-tech military systems. The
proposed TGP is a planar, thermal expansion matched heat
spreader that is capable of moving heat from multiple
chips to a remote thermal sink. DARPA’s final goals
require the TGP to have an effective conductivity of
20,000 W/mK, operate at 20g, with minimal fluid loss of
less than 0.1%/year and in a large ultra-thin planar package
of 10cmx20cm, no thicker than 1mm. The proposed TGP
is based on a heat pipe architecture[2], whereby the
enhanced transport of heat is made possible by applying
nanoengineered surfaces to the evaporator, wick, and
condenser surfaces. Ultra-low thermal resistances are
engineered using superhydrophilic and superhydrophobic
nanostructures on the interior surfaces of the TGP
envelope. The final TGP design will be easily integrated
into existing printed circuit board manufacturing
technology. In this paper, we present the transport design,
fabrication and packaging techniques, and finally a novel
fluorescence imaging technique to visualize the capillary
flow in these nanostructured wicks. |
| first_indexed | 2024-09-23T15:44:33Z |
| format | Article |
| id | mit-1721.1/64411 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T15:44:33Z |
| publishDate | 2011 |
| publisher | Nano Science and Technology Institute |
| record_format | dspace |
| spelling | mit-1721.1/644112022-09-29T15:51:05Z Engineered Nanostructures for High Thermal Conductivity Substrates Varanasi, Kripa K. Chamarthy, Pramod Chauhan, Shakti de Bock, Peter Deng, Tao Kulkarni, Ambarish Mandrusiak, Gary Rush, Brian Russ, Boris Denault, Lauraine Weaver, Stanton Gerner, Frank M. Leland, Quinn Yerkes, Kirk Massachusetts Institute of Technology. Department of Mechanical Engineering Varanasi, Kripa K. Varanasi, Kripa K. In the DARPA Thermal Ground Plane (TGP) program[1],we are developing a new thermal technology that will enable a monumental thermal technological leap to an entirely new class of electronics, particularly electronics for use in high-tech military systems. The proposed TGP is a planar, thermal expansion matched heat spreader that is capable of moving heat from multiple chips to a remote thermal sink. DARPA’s final goals require the TGP to have an effective conductivity of 20,000 W/mK, operate at 20g, with minimal fluid loss of less than 0.1%/year and in a large ultra-thin planar package of 10cmx20cm, no thicker than 1mm. The proposed TGP is based on a heat pipe architecture[2], whereby the enhanced transport of heat is made possible by applying nanoengineered surfaces to the evaporator, wick, and condenser surfaces. Ultra-low thermal resistances are engineered using superhydrophilic and superhydrophobic nanostructures on the interior surfaces of the TGP envelope. The final TGP design will be easily integrated into existing printed circuit board manufacturing technology. In this paper, we present the transport design, fabrication and packaging techniques, and finally a novel fluorescence imaging technique to visualize the capillary flow in these nanostructured wicks. United States. Defense Advanced Research Projects Agency (SSC SD Contract No. N66001-08-C-2008) 2011-06-10T18:06:00Z 2011-06-10T18:06:00Z 2009-05 Article http://purl.org/eprint/type/ConferencePaper http://hdl.handle.net/1721.1/64411 Varanasi, Kripa K. et al. "Engineered Nanostructures for High Thermal Conductivity Substrates" Nanotechnology Conference and Trade Show (2009 : Houston, Tex.) https://orcid.org/0000-0002-6846-152X en_US http://www.nsti.org/Nanotech2009/abs.html?i=870 Nanotechnology Conference and Trade Show (Expo) (2009 : Houston, Tex.) Creative Commons Attribution-Noncommercial-Share Alike 3.0 http://creativecommons.org/licenses/by-nc-sa/3.0/ application/pdf Nano Science and Technology Institute MIT web domain |
| spellingShingle | Varanasi, Kripa K. Chamarthy, Pramod Chauhan, Shakti de Bock, Peter Deng, Tao Kulkarni, Ambarish Mandrusiak, Gary Rush, Brian Russ, Boris Denault, Lauraine Weaver, Stanton Gerner, Frank M. Leland, Quinn Yerkes, Kirk Engineered Nanostructures for High Thermal Conductivity Substrates |
| title | Engineered Nanostructures for High Thermal Conductivity Substrates |
| title_full | Engineered Nanostructures for High Thermal Conductivity Substrates |
| title_fullStr | Engineered Nanostructures for High Thermal Conductivity Substrates |
| title_full_unstemmed | Engineered Nanostructures for High Thermal Conductivity Substrates |
| title_short | Engineered Nanostructures for High Thermal Conductivity Substrates |
| title_sort | engineered nanostructures for high thermal conductivity substrates |
| url | http://hdl.handle.net/1721.1/64411 https://orcid.org/0000-0002-6846-152X |
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