Test Generation Guided Design for Testability
This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) settin...
| Main Author: | |
|---|---|
| Language: | en_US |
| Published: |
2004
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1721.1/6837 |
| _version_ | 1826195212882411520 |
|---|---|
| author | Wu, Peng |
| author_facet | Wu, Peng |
| author_sort | Wu, Peng |
| collection | MIT |
| description | This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) setting design for testability in the context of test generation (TG), (2) using failures during FG to focus on testability problems, and (3) relating circuit modifications directly to the failures. A natural functionality set is used to represent the maximum functionalities that a component can have. The current implementation has only primitive domain knowledge and needs other work as well. However, armed with the knowledge of TG, it has already demonstrated its ability and produced some interesting results on a simple microprocessor. |
| first_indexed | 2024-09-23T10:09:10Z |
| id | mit-1721.1/6837 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T10:09:10Z |
| publishDate | 2004 |
| record_format | dspace |
| spelling | mit-1721.1/68372019-04-12T08:32:26Z Test Generation Guided Design for Testability Wu, Peng artificial intelligence knowledge representation testsgeneration knowledge-based systems VLSI design for testability This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) setting design for testability in the context of test generation (TG), (2) using failures during FG to focus on testability problems, and (3) relating circuit modifications directly to the failures. A natural functionality set is used to represent the maximum functionalities that a component can have. The current implementation has only primitive domain knowledge and needs other work as well. However, armed with the knowledge of TG, it has already demonstrated its ability and produced some interesting results on a simple microprocessor. 2004-10-20T20:00:56Z 2004-10-20T20:00:56Z 1988-07-01 AITR-1051 http://hdl.handle.net/1721.1/6837 en_US AITR-1051 129 p. 13659756 bytes 5291048 bytes application/postscript application/pdf application/postscript application/pdf |
| spellingShingle | artificial intelligence knowledge representation testsgeneration knowledge-based systems VLSI design for testability Wu, Peng Test Generation Guided Design for Testability |
| title | Test Generation Guided Design for Testability |
| title_full | Test Generation Guided Design for Testability |
| title_fullStr | Test Generation Guided Design for Testability |
| title_full_unstemmed | Test Generation Guided Design for Testability |
| title_short | Test Generation Guided Design for Testability |
| title_sort | test generation guided design for testability |
| topic | artificial intelligence knowledge representation testsgeneration knowledge-based systems VLSI design for testability |
| url | http://hdl.handle.net/1721.1/6837 |
| work_keys_str_mv | AT wupeng testgenerationguideddesignfortestability |