All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits

Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates spatial variation in digital circuit performance: we describe a test-chip in 90 nm CMOS containing all-digital me...

Ful tanımlama

Detaylı Bibliyografya
Asıl Yazarlar: Drego, Nigel A., Chandrakasan, Anantha P., Boning, Duane S.
Diğer Yazarlar: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Materyal Türü: Makale
Dil:en_US
Baskı/Yayın Bilgisi: Institute of Electrical and Electronics Engineers (IEEE) 2012
Online Erişim:http://hdl.handle.net/1721.1/69949
https://orcid.org/0000-0002-5977-2748
https://orcid.org/0000-0002-0417-445X