All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits
Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates spatial variation in digital circuit performance: we describe a test-chip in 90 nm CMOS containing all-digital me...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/69949 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0002-0417-445X |