ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores

ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores

This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability. Both coherence mechanisms co-exist in the hardware and ARCc enables seamless transition between...

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Bibliographic Details
Main Authors: Khan, Omer, Hoffmann, Henry Christian, Lis, Mieszko, Hijaz, Farrukh, Agarwal, Anant, Devadas, Srinivas
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers 2012
Online Access:http://hdl.handle.net/1721.1/71262
https://orcid.org/0000-0001-8253-7714
https://orcid.org/0000-0002-7015-4262
https://orcid.org/0000-0001-5490-2323

Internet

http://hdl.handle.net/1721.1/71262
https://orcid.org/0000-0001-8253-7714
https://orcid.org/0000-0002-7015-4262
https://orcid.org/0000-0001-5490-2323

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