Analytical model for RF power performance of deeply scaled CMOS devices

This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under...

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Main Authors: Gogineni, Usha, del Alamo, Jesus A., Valdes-Garcia, Alberto
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers (IEEE) 2012
Online Access:http://hdl.handle.net/1721.1/71960
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author Gogineni, Usha
del Alamo, Jesus A.
Valdes-Garcia, Alberto
author2 Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
author_facet Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Gogineni, Usha
del Alamo, Jesus A.
Valdes-Garcia, Alberto
author_sort Gogineni, Usha
collection MIT
description This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations.
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spelling mit-1721.1/719602022-09-28T18:08:35Z Analytical model for RF power performance of deeply scaled CMOS devices Gogineni, Usha del Alamo, Jesus A. Valdes-Garcia, Alberto Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science del Alamo, Jesus A. Gogineni, Usha del Alamo, Jesus A. This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations. Semiconductor Research Corporation. (Grant Number 2007-HJ-1661) 2012-08-02T18:45:26Z 2012-08-02T18:45:26Z 2011-07 2011-06 Article http://purl.org/eprint/type/ConferencePaper 978-1-4244-8291-7 978-1-4244-8293-1 1529-2517 http://hdl.handle.net/1721.1/71960 Gogineni, Usha, Jesus del Alamo, and Alberto Valdes-Garcia. “Analytical Model for RF Power Performance of Deeply Scaled CMOS Devices.” IEEE Radio Frequency Integrated Circuits Symposium, 2011. 2011 1–4. en_US http://dx.doi.org/10.1109/RFIC.2011.5940647 2011 IEEE Radio Frequency Integrated Circuits Symposium Creative Commons Attribution-Noncommercial-Share Alike 3.0 http://creativecommons.org/licenses/by-nc-sa/3.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) MIT web domain
spellingShingle Gogineni, Usha
del Alamo, Jesus A.
Valdes-Garcia, Alberto
Analytical model for RF power performance of deeply scaled CMOS devices
title Analytical model for RF power performance of deeply scaled CMOS devices
title_full Analytical model for RF power performance of deeply scaled CMOS devices
title_fullStr Analytical model for RF power performance of deeply scaled CMOS devices
title_full_unstemmed Analytical model for RF power performance of deeply scaled CMOS devices
title_short Analytical model for RF power performance of deeply scaled CMOS devices
title_sort analytical model for rf power performance of deeply scaled cmos devices
url http://hdl.handle.net/1721.1/71960
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