Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts and broadcasts. We first define and analyze the theoretical limits of a mesh NoC in latency, thro...

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Bibliographic Details
Main Authors: Park, Sunghyun, Krishna, Tushar, Chen, Chia-Hsin, Daya, Bhavya Kishor, Chandrakasan, Anantha P., Peh, Li-Shiuan
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:en_US
Published: Association for Computing Machinery (ACM) 2012
Online Access:http://hdl.handle.net/1721.1/72477
https://orcid.org/0000-0001-9010-6519
https://orcid.org/0000-0002-3383-1535
https://orcid.org/0000-0002-5977-2748
https://orcid.org/0000-0003-1284-6620

Internet

http://hdl.handle.net/1721.1/72477
https://orcid.org/0000-0001-9010-6519
https://orcid.org/0000-0002-3383-1535
https://orcid.org/0000-0002-5977-2748
https://orcid.org/0000-0003-1284-6620

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