Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit...
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Association for Computing Machinery (ACM)
2012
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| Online Access: | http://hdl.handle.net/1721.1/72480 https://orcid.org/0000-0001-9010-6519 https://orcid.org/0000-0003-1284-6620 |
| _version_ | 1826194267390869504 |
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| author | Aisopos, Konstantinos Chen, Chia-Hsin Peh, Li-Shiuan |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Aisopos, Konstantinos Chen, Chia-Hsin Peh, Li-Shiuan |
| author_sort | Aisopos, Konstantinos |
| collection | MIT |
| description | Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs. |
| first_indexed | 2024-09-23T09:53:26Z |
| format | Article |
| id | mit-1721.1/72480 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T09:53:26Z |
| publishDate | 2012 |
| publisher | Association for Computing Machinery (ACM) |
| record_format | dspace |
| spelling | mit-1721.1/724802022-09-26T14:20:56Z Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip Aisopos, Konstantinos Chen, Chia-Hsin Peh, Li-Shiuan Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Peh, Li-Shiuan Aisopos, Konstanti Chen, Chia-Hsin Peh, Li-Shiuan Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs. GigaScale Systems Research Center Focus Center Research Program. Focus Center for Circuit & System Solutions. Semiconductor Research Corporation. Interconnect Focus Center 2012-08-30T18:19:34Z 2012-08-30T18:19:34Z 2011-06 Article http://purl.org/eprint/type/ConferencePaper 978-1-4503-0636-2 http://hdl.handle.net/1721.1/72480 Konstantinos Aisopos, Chia-Hsin Chen, and Li-Shiuan Peh. 2011. Enabling system-level modeling of variation-induced faults in networks-on-chips. In Proceedings of the 48th Design Automation Conference (DAC '11). ACM, New York, NY, USA, 930-935. https://orcid.org/0000-0001-9010-6519 https://orcid.org/0000-0003-1284-6620 en_US http://dx.doi.org/10.1145/2024724.2024931 Proceedings of the 48th Design Automation Conference (DAC '11) Creative Commons Attribution-Noncommercial-Share Alike 3.0 http://creativecommons.org/licenses/by-nc-sa/3.0/ application/pdf Association for Computing Machinery (ACM) MIT web domain |
| spellingShingle | Aisopos, Konstantinos Chen, Chia-Hsin Peh, Li-Shiuan Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip |
| title | Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip |
| title_full | Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip |
| title_fullStr | Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip |
| title_full_unstemmed | Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip |
| title_short | Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip |
| title_sort | enabling system level modeling of variation induced faults in networks on chip |
| url | http://hdl.handle.net/1721.1/72480 https://orcid.org/0000-0001-9010-6519 https://orcid.org/0000-0003-1284-6620 |
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