Scalable, accurate multicore simulation in the 1000-core era

Scalable, accurate multicore simulation in the 1000-core era

We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs bet...

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Bibliographic Details
Main Authors: Lis, Mieszko, Ren, Pengju, Cho, Myong Hyon, Shim, Keun Sup, Fletcher, Christopher Wardlaw, Khan, Omer, Devadas, Srinivas
Other Authors: Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers (IEEE) 2012
Online Access:http://hdl.handle.net/1721.1/73118
https://orcid.org/0000-0001-8253-7714
https://orcid.org/0000-0001-5490-2323
https://orcid.org/0000-0003-1467-2150

Internet

http://hdl.handle.net/1721.1/73118
https://orcid.org/0000-0001-8253-7714
https://orcid.org/0000-0001-5490-2323
https://orcid.org/0000-0003-1467-2150

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