Discrete-time, cyclostationary phase-locked loop model for jitter analysis
Timing jitter is one of the most significant phase-locked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cy...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/74124 |
| _version_ | 1826217030096781312 |
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| author | Vamvakos, Socrates D. Stojanovic, Vladimir Marko Nikolic, Borivoje |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Vamvakos, Socrates D. Stojanovic, Vladimir Marko Nikolic, Borivoje |
| author_sort | Vamvakos, Socrates D. |
| collection | MIT |
| description | Timing jitter is one of the most significant phase-locked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cyclostationary PLL model for jitter analysis is proposed, which accounts for the cyclostationary nature of noise injected into the loop at various PLL components. The model also predicts the aliasing of jitter due to the downsampling and upsampling of frequencies around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a 3[superscript rd]-order PLL. |
| first_indexed | 2024-09-23T16:56:56Z |
| format | Article |
| id | mit-1721.1/74124 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T16:56:56Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/741242022-10-03T09:20:19Z Discrete-time, cyclostationary phase-locked loop model for jitter analysis Vamvakos, Socrates D. Stojanovic, Vladimir Marko Nikolic, Borivoje Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Stojanovic, Vladimir Marko Timing jitter is one of the most significant phase-locked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cyclostationary PLL model for jitter analysis is proposed, which accounts for the cyclostationary nature of noise injected into the loop at various PLL components. The model also predicts the aliasing of jitter due to the downsampling and upsampling of frequencies around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a 3[superscript rd]-order PLL. 2012-10-18T20:55:33Z 2012-10-18T20:55:33Z 2009-10 2009-09 Article http://purl.org/eprint/type/ConferencePaper 978-1-4244-4073-3 978-1-4244-4071-9 http://hdl.handle.net/1721.1/74124 Vamvakos, Socrates D., Vladimir Stojanovic, and Borivoje Nikolic. “Discrete-time, Cyclostationary Phase-locked Loop Model for Jitter Analysis.” IEEE, 2009. 637–640. © 2012 IEEE en_US http://dx.doi.org/10.1109/CICC.2009.5280745 Proceedings of the Custom Integrated Circuits Conference, 2009 Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers (IEEE) IEEE |
| spellingShingle | Vamvakos, Socrates D. Stojanovic, Vladimir Marko Nikolic, Borivoje Discrete-time, cyclostationary phase-locked loop model for jitter analysis |
| title | Discrete-time, cyclostationary phase-locked loop model for jitter analysis |
| title_full | Discrete-time, cyclostationary phase-locked loop model for jitter analysis |
| title_fullStr | Discrete-time, cyclostationary phase-locked loop model for jitter analysis |
| title_full_unstemmed | Discrete-time, cyclostationary phase-locked loop model for jitter analysis |
| title_short | Discrete-time, cyclostationary phase-locked loop model for jitter analysis |
| title_sort | discrete time cyclostationary phase locked loop model for jitter analysis |
| url | http://hdl.handle.net/1721.1/74124 |
| work_keys_str_mv | AT vamvakossocratesd discretetimecyclostationaryphaselockedloopmodelforjitteranalysis AT stojanovicvladimirmarko discretetimecyclostationaryphaselockedloopmodelforjitteranalysis AT nikolicborivoje discretetimecyclostationaryphaselockedloopmodelforjitteranalysis |