A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing
The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The grea...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
2004
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1721.1/7455 |
| _version_ | 1811082183348060160 |
|---|---|
| author | Noh, Kyungyoon Saka, Nannaji Chun, Jung-Hoon |
| author_facet | Noh, Kyungyoon Saka, Nannaji Chun, Jung-Hoon |
| author_sort | Noh, Kyungyoon |
| collection | MIT |
| description | The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates
wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested. |
| first_indexed | 2024-09-23T11:58:54Z |
| format | Article |
| id | mit-1721.1/7455 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T11:58:54Z |
| publishDate | 2004 |
| record_format | dspace |
| spelling | mit-1721.1/74552019-04-11T02:45:30Z A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing Noh, Kyungyoon Saka, Nannaji Chun, Jung-Hoon Chemical mechanical polishing Cu dishing Semiconductor manufacturing The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested. Singapore-MIT Alliance (SMA) 2004-12-14T20:21:21Z 2004-12-14T20:21:21Z 2005-01 Article http://hdl.handle.net/1721.1/7455 en Innovation in Manufacturing Systems and Technology (IMST); 381488 bytes application/pdf application/pdf |
| spellingShingle | Chemical mechanical polishing Cu dishing Semiconductor manufacturing Noh, Kyungyoon Saka, Nannaji Chun, Jung-Hoon A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing |
| title | A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing |
| title_full | A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing |
| title_fullStr | A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing |
| title_full_unstemmed | A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing |
| title_short | A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing |
| title_sort | multi scale model for copper dishing in chemical mechanical polishing |
| topic | Chemical mechanical polishing Cu dishing Semiconductor manufacturing |
| url | http://hdl.handle.net/1721.1/7455 |
| work_keys_str_mv | AT nohkyungyoon amultiscalemodelforcopperdishinginchemicalmechanicalpolishing AT sakanannaji amultiscalemodelforcopperdishinginchemicalmechanicalpolishing AT chunjunghoon amultiscalemodelforcopperdishinginchemicalmechanicalpolishing AT nohkyungyoon multiscalemodelforcopperdishinginchemicalmechanicalpolishing AT sakanannaji multiscalemodelforcopperdishinginchemicalmechanicalpolishing AT chunjunghoon multiscalemodelforcopperdishinginchemicalmechanicalpolishing |