Code compaction and parallelization for VLIW/DSP chip architectures
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
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Formato: | Tesis |
Lenguaje: | eng |
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Massachusetts Institute of Technology
2013
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Acceso en línea: | http://hdl.handle.net/1721.1/80111 |