Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/8082 |
| _version_ | 1826191772936568832 |
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| author | Park, Tae Hong, 1973- |
| author2 | Duane S. Boning. |
| author_facet | Duane S. Boning. Park, Tae Hong, 1973- |
| author_sort | Park, Tae Hong, 1973- |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002. |
| first_indexed | 2024-09-23T09:01:24Z |
| format | Thesis |
| id | mit-1721.1/8082 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:01:24Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/80822019-04-10T20:14:49Z Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits Park, Tae Hong, 1973- Duane S. Boning. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002. Includes bibliographical references (p. 173-176). Copper metallization has emerged as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the polished surface exhibit pattern dependent topography. In this thesis, a methodology for the characterization and modeling of pattern dependent problems in copper interconnect topography is developed. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semi-empirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, line width distributions, and line length are extracted for each cell in a 40 gm by 40 tm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 A for array height and around 500 A for step height. This methodology provides the first known chip-scale prediction of electroplated topography. For pattern dependencies in copper CMP, this thesis focuses on the development of test structures and masks (including multi-level structures) to identify key pattern effects in both single-level and multi-level polishing. (cont.) Especially for the multi-level studies, electrical test structures and measurements in addition to surface profile scans are seen to be important in accurately determining thickness variations. The developed test vehicle and characterization of copper dishing and oxide erosion serve as a basis for further pattern dependent model development. Finally, integration of electroplating and CMP chip-scale models is illustrated; the simulated step and array heights as well as topography pattern density are used as an input for the initial starting topography for CMP simulation of subsequent polishing profile evolution. by Tae Hong Park. Ph.D. 2005-08-24T20:11:09Z 2005-08-24T20:11:09Z 2002 2002 Thesis http://hdl.handle.net/1721.1/8082 51198259 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 204 p. 18620108 bytes 18619867 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Park, Tae Hong, 1973- Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits |
| title | Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits |
| title_full | Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits |
| title_fullStr | Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits |
| title_full_unstemmed | Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits |
| title_short | Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits |
| title_sort | characterization and modeling of pattern dependencies in copper interconnects for integrated circuits |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/8082 |
| work_keys_str_mv | AT parktaehong1973 characterizationandmodelingofpatterndependenciesincopperinterconnectsforintegratedcircuits |