Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs
A simulation methodology for ultra-scaled InAs quantum well field-effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, a...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2014
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| Online Access: | http://hdl.handle.net/1721.1/86094 |
| _version_ | 1826195977484107776 |
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| author | Kharche, Neerav Klimeck, Gerhard Kim, Dae-Hyun Luisier, Mathieu del Alamo, Jesus A. |
| author2 | Massachusetts Institute of Technology. Microsystems Technology Laboratories |
| author_facet | Massachusetts Institute of Technology. Microsystems Technology Laboratories Kharche, Neerav Klimeck, Gerhard Kim, Dae-Hyun Luisier, Mathieu del Alamo, Jesus A. |
| author_sort | Kharche, Neerav |
| collection | MIT |
| description | A simulation methodology for ultra-scaled InAs quantum well field-effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp[superscript 3]d[superscript 5]s* tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass-based ballistic quantum transport model is employed to simulate three-terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I-V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage current of the QWFETs, i) the geometry of the gate contact (curved or square) and ii) the Schottky barrier height at the gate metal contact. In addition to pushing the threshold voltage toward an enhancement mode operation, a higher Schottky barrier at gate metal contact can help suppress the gate leakage and enable aggressive insulator scaling. |
| first_indexed | 2024-09-23T10:18:53Z |
| format | Article |
| id | mit-1721.1/86094 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T10:18:53Z |
| publishDate | 2014 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/860942022-09-26T17:10:01Z Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs Kharche, Neerav Klimeck, Gerhard Kim, Dae-Hyun Luisier, Mathieu del Alamo, Jesus A. Massachusetts Institute of Technology. Microsystems Technology Laboratories del Alamo, Jesus A. A simulation methodology for ultra-scaled InAs quantum well field-effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp[superscript 3]d[superscript 5]s* tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass-based ballistic quantum transport model is employed to simulate three-terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I-V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage current of the QWFETs, i) the geometry of the gate contact (curved or square) and ii) the Schottky barrier height at the gate metal contact. In addition to pushing the threshold voltage toward an enhancement mode operation, a higher Schottky barrier at gate metal contact can help suppress the gate leakage and enable aggressive insulator scaling. Semiconductor Research Corporation Microelectronics Advanced Research Corporation (MARCO) (Focus Center on Materials, Structures, and Devices) National Science Foundation (U.S.) 2014-04-11T13:22:46Z 2014-04-11T13:22:46Z 2011-05 2011-03 Article http://purl.org/eprint/type/JournalArticle 0018-9383 1557-9646 http://hdl.handle.net/1721.1/86094 Kharche, Neerav, Gerhard Klimeck, Dae-Hyun Kim, Jesus A. del Alamo, and Mathieu Luisier. “Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs.” IEEE Transactions on Electron Devices 58, no. 7 (n.d.): 1963–1971. en_US http://dx.doi.org/10.1109/ted.2011.2144986 IEEE Transactions on Electron Devices Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) arXiv |
| spellingShingle | Kharche, Neerav Klimeck, Gerhard Kim, Dae-Hyun Luisier, Mathieu del Alamo, Jesus A. Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs |
| title | Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs |
| title_full | Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs |
| title_fullStr | Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs |
| title_full_unstemmed | Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs |
| title_short | Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs |
| title_sort | multiscale metrology and optimization of ultra scaled inas quantum well fets |
| url | http://hdl.handle.net/1721.1/86094 |
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