A general technique for deterministic model-cycle-level debugging
Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2014
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| Online Access: | http://hdl.handle.net/1721.1/90485 https://orcid.org/0000-0002-9737-2366 https://orcid.org/0000-0003-0599-0800 |