A general technique for deterministic model-cycle-level debugging
Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2014
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| Online Access: | http://hdl.handle.net/1721.1/90485 https://orcid.org/0000-0002-9737-2366 https://orcid.org/0000-0003-0599-0800 |
| _version_ | 1826202021979488256 |
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| author | Khan, Asif Imtiaz Vijayaraghavan, Muralidaran Mithal, Arvind |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Khan, Asif Imtiaz Vijayaraghavan, Muralidaran Mithal, Arvind |
| author_sort | Khan, Asif Imtiaz |
| collection | MIT |
| description | Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the model-cycle boundaries if only implementation-cycle-level control and information is provided. A good debugging facility needs to provide: complete control over the functioning of the target design being simulated; fast and easy access to all the significant target design state for both monitoring and modification; and some means of accomplishing deterministic execution when the target design is a multicore processor running a parallel application. Moreover, these features need to be provided in a manner which does not incur substantial resource and performance penalties. In this paper, we present a debugging technique based on the LI-BDN theory. We show how the technique facilitates deterministic model-cycle-level debugging. We used it to build the debugging infrastructure for Arete, which is an FPGA-based cycle-accurate multicore simulator. The resource and performance penalties of our debugging technique are minimal; in Arete the debugging infrastructure has area and performance overheads of 5% and 6%, respectively. |
| first_indexed | 2024-09-23T12:00:39Z |
| format | Article |
| id | mit-1721.1/90485 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T12:00:39Z |
| publishDate | 2014 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/904852022-09-27T23:27:33Z A general technique for deterministic model-cycle-level debugging Khan, Asif Imtiaz Vijayaraghavan, Muralidaran Mithal, Arvind Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Khan, Asif Imtiaz Vijayaraghavan, Muralidaran Mithal, Arvind Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the model-cycle boundaries if only implementation-cycle-level control and information is provided. A good debugging facility needs to provide: complete control over the functioning of the target design being simulated; fast and easy access to all the significant target design state for both monitoring and modification; and some means of accomplishing deterministic execution when the target design is a multicore processor running a parallel application. Moreover, these features need to be provided in a manner which does not incur substantial resource and performance penalties. In this paper, we present a debugging technique based on the LI-BDN theory. We show how the technique facilitates deterministic model-cycle-level debugging. We used it to build the debugging infrastructure for Arete, which is an FPGA-based cycle-accurate multicore simulator. The resource and performance penalties of our debugging technique are minimal; in Arete the debugging infrastructure has area and performance overheads of 5% and 6%, respectively. IBM Research 2014-09-30T17:05:16Z 2014-09-30T17:05:16Z 2012-07 Article http://purl.org/eprint/type/ConferencePaper 978-1-4673-1313-1 978-1-4673-1314-8 http://hdl.handle.net/1721.1/90485 Khan, Asif, Muralidaran Vijayaraghavan, and Mithal Arvind. “A General Technique for Deterministic Model-Cycle-Level Debugging.” Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012) (July 2012). https://orcid.org/0000-0002-9737-2366 https://orcid.org/0000-0003-0599-0800 en_US http://dx.doi.org/10.1109/MEMCOD.2012.6292307 Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012) Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) MIT web domain |
| spellingShingle | Khan, Asif Imtiaz Vijayaraghavan, Muralidaran Mithal, Arvind A general technique for deterministic model-cycle-level debugging |
| title | A general technique for deterministic model-cycle-level debugging |
| title_full | A general technique for deterministic model-cycle-level debugging |
| title_fullStr | A general technique for deterministic model-cycle-level debugging |
| title_full_unstemmed | A general technique for deterministic model-cycle-level debugging |
| title_short | A general technique for deterministic model-cycle-level debugging |
| title_sort | general technique for deterministic model cycle level debugging |
| url | http://hdl.handle.net/1721.1/90485 https://orcid.org/0000-0002-9737-2366 https://orcid.org/0000-0003-0599-0800 |
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