Optimization of Integrated Transistors for Very High Frequency DC-DC Converters
This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting lay...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2014
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| Online Access: | http://hdl.handle.net/1721.1/90546 https://orcid.org/0000-0002-0746-6191 |
| _version_ | 1811081571631890432 |
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| author | Sagneri, Anthony D. Anderson, David I. Perreault, David J. |
| author2 | Massachusetts Institute of Technology. Laboratory for Electromagnetic and Electronic Systems |
| author_facet | Massachusetts Institute of Technology. Laboratory for Electromagnetic and Electronic Systems Sagneri, Anthony D. Anderson, David I. Perreault, David J. |
| author_sort | Sagneri, Anthony D. |
| collection | MIT |
| description | This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout versus loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50-MHz converter, resulting in a 54% reduction in power loss over a hand-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 3-μm gate length in 20-V design rules is validated at 35 V, offering reduced parasitic resistance and capacitance, as compared to the 5.5-μm device. Compared to the original design, loss is up to 75% lower in the example application. |
| first_indexed | 2024-09-23T11:48:45Z |
| format | Article |
| id | mit-1721.1/90546 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T11:48:45Z |
| publishDate | 2014 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/905462022-09-27T22:04:39Z Optimization of Integrated Transistors for Very High Frequency DC-DC Converters Sagneri, Anthony D. Anderson, David I. Perreault, David J. Massachusetts Institute of Technology. Laboratory for Electromagnetic and Electronic Systems Massachusetts Institute of Technology. School of Engineering Perreault, David J. This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout versus loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50-MHz converter, resulting in a 54% reduction in power loss over a hand-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 3-μm gate length in 20-V design rules is validated at 35 V, offering reduced parasitic resistance and capacitance, as compared to the 5.5-μm device. Compared to the original design, loss is up to 75% lower in the example application. 2014-10-02T17:24:29Z 2014-10-02T17:24:29Z 2013-07 2012-07 Article http://purl.org/eprint/type/JournalArticle 0885-8993 1941-0107 http://hdl.handle.net/1721.1/90546 Sagneri, Anthony D., David I. Anderson, and David J. Perreault. “Optimization of Integrated Transistors for Very High Frequency DC-DC Converters.” IEEE Trans. Power Electron. 28, no. 7 (July 2013): 3614–3626. https://orcid.org/0000-0002-0746-6191 en_US http://dx.doi.org/10.1109/TPEL.2012.2222048 IEEE Transactions on Power Electronics Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) MIT web domain |
| spellingShingle | Sagneri, Anthony D. Anderson, David I. Perreault, David J. Optimization of Integrated Transistors for Very High Frequency DC-DC Converters |
| title | Optimization of Integrated Transistors for Very High Frequency DC-DC Converters |
| title_full | Optimization of Integrated Transistors for Very High Frequency DC-DC Converters |
| title_fullStr | Optimization of Integrated Transistors for Very High Frequency DC-DC Converters |
| title_full_unstemmed | Optimization of Integrated Transistors for Very High Frequency DC-DC Converters |
| title_short | Optimization of Integrated Transistors for Very High Frequency DC-DC Converters |
| title_sort | optimization of integrated transistors for very high frequency dc dc converters |
| url | http://hdl.handle.net/1721.1/90546 https://orcid.org/0000-0002-0746-6191 |
| work_keys_str_mv | AT sagnerianthonyd optimizationofintegratedtransistorsforveryhighfrequencydcdcconverters AT andersondavidi optimizationofintegratedtransistorsforveryhighfrequencydcdcconverters AT perreaultdavidj optimizationofintegratedtransistorsforveryhighfrequencydcdcconverters |