Jigsaw: Scalable software-defined caches
Shared last-level caches, widely used in chip-multi-processors (CMPs), face two fundamental limitations. First, the latency and energy of shared caches degrade as the system scales up. Second, when multiple workloads share the CMP, they suffer from interference in shared cache accesses. Unfortunatel...
| Main Authors: | , |
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| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2014
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| Online Access: | http://hdl.handle.net/1721.1/90818 https://orcid.org/0000-0002-2453-2904 https://orcid.org/0000-0002-6057-9769 |