A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration
A 12-bit 50MS/s SAR ADC implemented in 65nm CMOS technology is presented. The design employs redundancy to relax the DAC settling requirement and to provide sufficient room for errors such that the static nonlinearity caused by capacitor mismatches can be digitally removed. The redundancy is incorpo...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2014
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| Online Access: | http://hdl.handle.net/1721.1/92432 https://orcid.org/0000-0002-7783-0403 https://orcid.org/0000-0002-0417-445X |