SMART: A Single-Cycle Reconfigurable NoC for SoC Applications
As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cyc...
| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/93236 https://orcid.org/0000-0001-9010-6519 https://orcid.org/0000-0001-7701-8303 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-1284-6620 |