SMART: A Single-Cycle Reconfigurable NoC for SoC Applications
As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cyc...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/93236 https://orcid.org/0000-0001-9010-6519 https://orcid.org/0000-0001-7701-8303 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-1284-6620 |
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| author | Park, Sunghyun Krishna, Tushar Subramanian, Suvinay Chandrakasan, Anantha P. Peh, Li-Shiuan Chen, Chia-Hsin |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Park, Sunghyun Krishna, Tushar Subramanian, Suvinay Chandrakasan, Anantha P. Peh, Li-Shiuan Chen, Chia-Hsin |
| author_sort | Park, Sunghyun |
| collection | MIT |
| description | As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8mm within a single cycle, i.e. 8 hops with 1mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC. |
| first_indexed | 2024-09-23T14:58:39Z |
| format | Article |
| id | mit-1721.1/93236 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T14:58:39Z |
| publishDate | 2015 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/932362022-10-01T23:42:56Z SMART: A Single-Cycle Reconfigurable NoC for SoC Applications Park, Sunghyun Krishna, Tushar Subramanian, Suvinay Chandrakasan, Anantha P. Peh, Li-Shiuan Chen, Chia-Hsin Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Chandrakasan, Anantha P. Park, Sunghyun Krishna, Tushar Subramanian, Suvinay Chandrakasan, Anantha P. Peh, Li-Shiuan Chen, Chia-Hsin As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8mm within a single cycle, i.e. 8 hops with 1mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC. United States. Defense Advanced Research Projects Agency. The Ubiquitous High-Performance Computing Program 2015-01-30T18:51:45Z 2015-01-30T18:51:45Z 2013-03 Article http://purl.org/eprint/type/ConferencePaper 9781467350716 1530-1591 http://hdl.handle.net/1721.1/93236 Chen, Chia-Hsin Owen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, and Li-Shiuan Peh. “SMART: A Single-Cycle Reconfigurable NoC for SoC Applications.” 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2013). https://orcid.org/0000-0001-9010-6519 https://orcid.org/0000-0001-7701-8303 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-1284-6620 en_US http://dx.doi.org/10.7873/DATE.2013.080 Proceedings of the 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) Chandrakasan |
| spellingShingle | Park, Sunghyun Krishna, Tushar Subramanian, Suvinay Chandrakasan, Anantha P. Peh, Li-Shiuan Chen, Chia-Hsin SMART: A Single-Cycle Reconfigurable NoC for SoC Applications |
| title | SMART: A Single-Cycle Reconfigurable NoC for SoC Applications |
| title_full | SMART: A Single-Cycle Reconfigurable NoC for SoC Applications |
| title_fullStr | SMART: A Single-Cycle Reconfigurable NoC for SoC Applications |
| title_full_unstemmed | SMART: A Single-Cycle Reconfigurable NoC for SoC Applications |
| title_short | SMART: A Single-Cycle Reconfigurable NoC for SoC Applications |
| title_sort | smart a single cycle reconfigurable noc for soc applications |
| url | http://hdl.handle.net/1721.1/93236 https://orcid.org/0000-0001-9010-6519 https://orcid.org/0000-0001-7701-8303 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-1284-6620 |
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