Ion traps fabricated in a CMOS foundry
We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-...
| Päätekijät: | , , , , , , |
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| Aineistotyyppi: | Artikkeli |
| Kieli: | en_US |
| Julkaistu: |
American Institute of Physics (AIP)
2015
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| Linkit: | http://hdl.handle.net/1721.1/99931 https://orcid.org/0000-0001-7296-523X https://orcid.org/0000-0002-0917-7182 https://orcid.org/0000-0003-0420-2235 |