Ion traps fabricated in a CMOS foundry
We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-...
| Main Authors: | , , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
American Institute of Physics (AIP)
2015
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| Online Access: | http://hdl.handle.net/1721.1/99931 https://orcid.org/0000-0001-7296-523X https://orcid.org/0000-0002-0917-7182 https://orcid.org/0000-0003-0420-2235 |
| Summary: | We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays. |
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