Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniques
Process variations are a major concern in today's chip design since they can significantly degrade chip performance. To predict such degradation, existing circuit and MEMS simulators rely on Monte Carlo algorithms, which are typically too slow. Therefore, novel fast stochastic simulators are hi...
| Main Authors: | , , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/99953 https://orcid.org/0000-0002-5880-3151 |