A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os

A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os

One memory-logic-integration design platform is developed in this paper with thermal reliability analysis provided for 2.5D through-silicon-interposer (TSI) and 3D through-silicon-via (TSV) based integrations. Temperature-dependent delay and power models have been developed at microarchitecture leve...

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Bibliographic Details
Main Authors: Wu, Sih-Sian, Wang, Kanwen, Manoj P. D, Sai, Ho, Tsung-Yi, Yu, Mingbin, Yu, Hao
Other Authors: School of Electrical and Electronic Engineering
Format: Conference Paper
Language:English
Published: 2015
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:https://hdl.handle.net/10356/105539
http://hdl.handle.net/10220/25512
http://dx.doi.org/10.7873/DATE.2014.190

Internet

https://hdl.handle.net/10356/105539
http://hdl.handle.net/10220/25512
http://dx.doi.org/10.7873/DATE.2014.190

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