An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators
Radix-2k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-22 multiple delay commutator architecture utilizing the advantages of the radix-22 algorithm, such as simple butterflies and less memory requirement....
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2019
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/105819 http://hdl.handle.net/10220/48771 http://dx.doi.org/10.1109/TCSI.2018.2831007 |