An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators
Radix-2k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-22 multiple delay commutator architecture utilizing the advantages of the radix-22 algorithm, such as simple butterflies and less memory requirement....
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| Format: | Journal Article |
| Language: | English |
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2019
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| Online Access: | https://hdl.handle.net/10356/105819 http://hdl.handle.net/10220/48771 http://dx.doi.org/10.1109/TCSI.2018.2831007 |
| _version_ | 1811678621710942208 |
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| author | Le Ba, Ngoc Kim, Tony Tae-Hyoung |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Le Ba, Ngoc Kim, Tony Tae-Hyoung |
| author_sort | Le Ba, Ngoc |
| collection | NTU |
| description | Radix-2k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-22 multiple delay commutator architecture utilizing the advantages of the radix-22 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data paths. Here, we propose an improved input scheduling algorithm based upon memory to eliminate energy required to shift data along the delay lines. A 1024-point FFT processor with two parallel data paths is implemented in 65-nm CMOS process technology. The FFT processor occupies an area of 3.6 mm2 , successfully operates in the supply voltage range from 0.4-1 V and the maximum clock frequency of 600 MHz. For low voltage, high performance applications, the processor is able to operate at 400 MHz and consumes 60.3 mW or 77.2 nJ/FFT generating 800 Msamples/s at 0.6 V supply. |
| first_indexed | 2024-10-01T02:56:11Z |
| format | Journal Article |
| id | ntu-10356/105819 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:56:11Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/1058192019-12-06T21:58:35Z An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators Le Ba, Ngoc Kim, Tony Tae-Hyoung School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Fast Fourier Transform Single Delay Feedback Radix-2k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-22 multiple delay commutator architecture utilizing the advantages of the radix-22 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data paths. Here, we propose an improved input scheduling algorithm based upon memory to eliminate energy required to shift data along the delay lines. A 1024-point FFT processor with two parallel data paths is implemented in 65-nm CMOS process technology. The FFT processor occupies an area of 3.6 mm2 , successfully operates in the supply voltage range from 0.4-1 V and the maximum clock frequency of 600 MHz. For low voltage, high performance applications, the processor is able to operate at 400 MHz and consumes 60.3 mW or 77.2 nJ/FFT generating 800 Msamples/s at 0.6 V supply. Accepted version 2019-06-14T06:59:20Z 2019-12-06T21:58:35Z 2019-06-14T06:59:20Z 2019-12-06T21:58:35Z 2018 Journal Article Le Ba, N., & Kim, T. T.-H. (2018). An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(10), 3291-3299. doi:10.1109/TCSI.2018.2831007 1549-8328 https://hdl.handle.net/10356/105819 http://hdl.handle.net/10220/48771 http://dx.doi.org/10.1109/TCSI.2018.2831007 en IEEE Transactions on Circuits and Systems I: Regular Papers © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCSI.2018.2831007 8 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Fast Fourier Transform Single Delay Feedback Le Ba, Ngoc Kim, Tony Tae-Hyoung An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators |
| title | An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators |
| title_full | An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators |
| title_fullStr | An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators |
| title_full_unstemmed | An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators |
| title_short | An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators |
| title_sort | area efficient 1024 point low power radix 22 fft processor with feed forward multiple delay commutators |
| topic | DRNTU::Engineering::Electrical and electronic engineering Fast Fourier Transform Single Delay Feedback |
| url | https://hdl.handle.net/10356/105819 http://hdl.handle.net/10220/48771 http://dx.doi.org/10.1109/TCSI.2018.2831007 |
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