Single-event-transient resilient memory for DSP in space applications
We present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes...
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| Format: | Conference Paper |
| Language: | English |
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2019
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| Online Access: | https://hdl.handle.net/10356/106084 http://hdl.handle.net/10220/49031 https://dx.doi.org/10.1109/ICDSP.2018.8631639 |
| _version_ | 1811697554288541696 |
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| author | Lwin, Ne Kyaw Zwa Sivaramakrishnan, H. Chong, Kwen-Siong Lin, Tong Shu, Wei Chang, Joseph S. |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Lwin, Ne Kyaw Zwa Sivaramakrishnan, H. Chong, Kwen-Siong Lin, Tong Shu, Wei Chang, Joseph S. |
| author_sort | Lwin, Ne Kyaw Zwa |
| collection | NTU |
| description | We present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes by combining a Triple-Interlocked Cell (TICE) SRAM cell array and a Triple Modular Redundancy (TMR) voter. The TICE SRAM cells therein self-correct SEUs and DEUs. The TMR voter eliminates SETs. Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEUand DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells. |
| first_indexed | 2024-10-01T07:57:06Z |
| format | Conference Paper |
| id | ntu-10356/106084 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:57:06Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/1060842019-12-06T22:04:17Z Single-event-transient resilient memory for DSP in space applications Lwin, Ne Kyaw Zwa Sivaramakrishnan, H. Chong, Kwen-Siong Lin, Tong Shu, Wei Chang, Joseph S. School of Electrical and Electronic Engineering 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP) Engineering::Electrical and electronic engineering Computer Architecture SRAM Cells We present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes by combining a Triple-Interlocked Cell (TICE) SRAM cell array and a Triple Modular Redundancy (TMR) voter. The TICE SRAM cells therein self-correct SEUs and DEUs. The TMR voter eliminates SETs. Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEUand DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells. MOE (Min. of Education, S’pore) Accepted version 2019-07-01T02:58:45Z 2019-12-06T22:04:17Z 2019-07-01T02:58:45Z 2019-12-06T22:04:17Z 2018-11-01 2018 Conference Paper Lwin, N. K. Z., Sivaramakrishnan, H., Chong, K. S., Lin, T., Shu, W., & Chang, J. S. (2018). Single-event-transient resilient memory for DSP in space applications. 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP). doi:10.1109/ICDSP.2018.8631639 https://hdl.handle.net/10356/106084 http://hdl.handle.net/10220/49031 https://dx.doi.org/10.1109/ICDSP.2018.8631639 210623 en © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/ICDSP.2018.8631639 5 p. application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering Computer Architecture SRAM Cells Lwin, Ne Kyaw Zwa Sivaramakrishnan, H. Chong, Kwen-Siong Lin, Tong Shu, Wei Chang, Joseph S. Single-event-transient resilient memory for DSP in space applications |
| title | Single-event-transient resilient memory for DSP in space applications |
| title_full | Single-event-transient resilient memory for DSP in space applications |
| title_fullStr | Single-event-transient resilient memory for DSP in space applications |
| title_full_unstemmed | Single-event-transient resilient memory for DSP in space applications |
| title_short | Single-event-transient resilient memory for DSP in space applications |
| title_sort | single event transient resilient memory for dsp in space applications |
| topic | Engineering::Electrical and electronic engineering Computer Architecture SRAM Cells |
| url | https://hdl.handle.net/10356/106084 http://hdl.handle.net/10220/49031 https://dx.doi.org/10.1109/ICDSP.2018.8631639 |
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