Performance characterisation and design issues of low voltage BiCMOS digital circuits

Performance characterisation and design issues of low voltage BiCMOS digital circuits

This report addresses the work done on the power and speed optimisation of 4 different BiCMOS gate structures using 3 sub-micron technologies; namely 1.5V/0.35um, 2.2V/0.5|im and 3.3V/0.8(im for several fan-in fan-out conditions. The BiCMOS structures studied in this project encompass the Bootstrapp...

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Bibliographic Details
Main Author: Cheong, Chee Seng.
Other Authors: School of Electrical and Electronic Engineering
Format: Thesis
Language:English
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:http://hdl.handle.net/10356/13150

Internet

http://hdl.handle.net/10356/13150

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