Research on CMOS latchup in quarter micron technology
This research work focuses on exploring the process techniques used to improve latchup immunity especially for 0.25 urn CMOS devices and investigating the behaviour of the parasitic bipolar transistors as the n+/p+ spacing is scaled to the sub-0.25 pm regime.
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| Format: | Thesis |
| Language: | English |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/13309 |