Research on CMOS latchup in quarter micron technology
This research work focuses on exploring the process techniques used to improve latchup immunity especially for 0.25 urn CMOS devices and investigating the behaviour of the parasitic bipolar transistors as the n+/p+ spacing is scaled to the sub-0.25 pm regime.
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/13309 |
| _version_ | 1811691032301010944 |
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| author | Leong, Kam Chew. |
| author2 | Liu, Po Ching |
| author_facet | Liu, Po Ching Leong, Kam Chew. |
| author_sort | Leong, Kam Chew. |
| collection | NTU |
| description | This research work focuses on exploring the process techniques used to improve latchup immunity especially for 0.25 urn CMOS devices and investigating the behaviour of the parasitic bipolar transistors as the n+/p+ spacing is scaled to the sub-0.25 pm regime. |
| first_indexed | 2024-10-01T06:13:26Z |
| format | Thesis |
| id | ntu-10356/13309 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:13:26Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/133092023-07-04T15:07:09Z Research on CMOS latchup in quarter micron technology Leong, Kam Chew. Liu, Po Ching School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This research work focuses on exploring the process techniques used to improve latchup immunity especially for 0.25 urn CMOS devices and investigating the behaviour of the parasitic bipolar transistors as the n+/p+ spacing is scaled to the sub-0.25 pm regime. Master of Engineering 2008-10-20T07:24:06Z 2008-10-20T07:24:06Z 1998 1998 Thesis http://hdl.handle.net/10356/13309 en 97 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Leong, Kam Chew. Research on CMOS latchup in quarter micron technology |
| title | Research on CMOS latchup in quarter micron technology |
| title_full | Research on CMOS latchup in quarter micron technology |
| title_fullStr | Research on CMOS latchup in quarter micron technology |
| title_full_unstemmed | Research on CMOS latchup in quarter micron technology |
| title_short | Research on CMOS latchup in quarter micron technology |
| title_sort | research on cmos latchup in quarter micron technology |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/13309 |
| work_keys_str_mv | AT leongkamchew researchoncmoslatchupinquartermicrontechnology |