A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS

A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS

Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a tripl...

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Bibliographic Details
Main Authors: Balachandran, Arya, Chen, Yong, Boon, Chirn Chye
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2020
Subjects:
Engineering::Electrical and electronic engineering
Channel Loss
CMOS Equalizer
Online Access:https://hdl.handle.net/10356/139733

Internet

https://hdl.handle.net/10356/139733

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