A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS
Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a tripl...
| Main Authors: | , , |
|---|---|
| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2020
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/139733 |
| _version_ | 1826113310424039424 |
|---|---|
| author | Balachandran, Arya Chen, Yong Boon, Chirn Chye |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Balachandran, Arya Chen, Yong Boon, Chirn Chye |
| author_sort | Balachandran, Arya |
| collection | NTU |
| description | Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a triple-gate control to achieve equalization over a range of channel loss resulting in an inductorless and area-efficient design. The triple-gate controls entail that a low-frequency equalization is achieved in addition to the intermediate and high-frequency equalization, at minimum area overhead. The prototype is realized in a 65-nm CMOS, occupying a compact active area of 0.013 mm2. The maximum equalization achieved is 21 dB at Nyquist with a measured peak-to-peak data jitter of 5.25 ps (0.17 unit interval) at 32 Gb/s for a 231 - 1 pseudorandom bit sequence signal. The measurement shows a vertical eye-opening recovery rate of up to 61% at 32 Gb/s, for a channel loss of 21 dB. The prototype exhibits a competitive power efficiency of 0.53 mW/Gb/s under a supply voltage of 1.2 V. |
| first_indexed | 2024-10-01T03:21:28Z |
| format | Journal Article |
| id | ntu-10356/139733 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:21:28Z |
| publishDate | 2020 |
| record_format | dspace |
| spelling | ntu-10356/1397332020-05-21T05:46:03Z A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS Balachandran, Arya Chen, Yong Boon, Chirn Chye School of Electrical and Electronic Engineering Integrated Circuit Design Centre of Excellence Engineering::Electrical and electronic engineering Channel Loss CMOS Equalizer Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a triple-gate control to achieve equalization over a range of channel loss resulting in an inductorless and area-efficient design. The triple-gate controls entail that a low-frequency equalization is achieved in addition to the intermediate and high-frequency equalization, at minimum area overhead. The prototype is realized in a 65-nm CMOS, occupying a compact active area of 0.013 mm2. The maximum equalization achieved is 21 dB at Nyquist with a measured peak-to-peak data jitter of 5.25 ps (0.17 unit interval) at 32 Gb/s for a 231 - 1 pseudorandom bit sequence signal. The measurement shows a vertical eye-opening recovery rate of up to 61% at 32 Gb/s, for a channel loss of 21 dB. The prototype exhibits a competitive power efficiency of 0.53 mW/Gb/s under a supply voltage of 1.2 V. MOE (Min. of Education, S’pore) 2020-05-21T05:46:03Z 2020-05-21T05:46:03Z 2017 Journal Article Balachandran, A., Chen, Y., & Boon, C. C. (2018). A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(3), 599-603. doi:10.1109/TVLSI.2017.2771429 1063-8210 https://hdl.handle.net/10356/139733 10.1109/TVLSI.2017.2771429 2-s2.0-85036571740 3 26 599 603 en IEEE Transactions on Very Large Scale Integration (VLSI) Systems © 2017 IEEE. All rights reserved. |
| spellingShingle | Engineering::Electrical and electronic engineering Channel Loss CMOS Equalizer Balachandran, Arya Chen, Yong Boon, Chirn Chye A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS |
| title | A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS |
| title_full | A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS |
| title_fullStr | A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS |
| title_full_unstemmed | A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS |
| title_short | A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS |
| title_sort | 0 013 mm2 0 53 mw gb s 32 gb s hybrid analog equalizer under 21 db channel loss in 65 nm cmos |
| topic | Engineering::Electrical and electronic engineering Channel Loss CMOS Equalizer |
| url | https://hdl.handle.net/10356/139733 |
| work_keys_str_mv | AT balachandranarya a0013mm2053mwgbs32gbshybridanalogequalizerunder21dbchannellossin65nmcmos AT chenyong a0013mm2053mwgbs32gbshybridanalogequalizerunder21dbchannellossin65nmcmos AT boonchirnchye a0013mm2053mwgbs32gbshybridanalogequalizerunder21dbchannellossin65nmcmos AT balachandranarya 0013mm2053mwgbs32gbshybridanalogequalizerunder21dbchannellossin65nmcmos AT chenyong 0013mm2053mwgbs32gbshybridanalogequalizerunder21dbchannellossin65nmcmos AT boonchirnchye 0013mm2053mwgbs32gbshybridanalogequalizerunder21dbchannellossin65nmcmos |