Uniform delayering of copper metallization
Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization remova...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
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2020
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/143510 |
| _version_ | 1826113254042107904 |
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| author | Siah, Yu Wen Hong, Y. J. Liu, Q. Kor, Katherine Hwee Boon Gan, C. L. |
| author2 | School of Materials Science and Engineering |
| author_facet | School of Materials Science and Engineering Siah, Yu Wen Hong, Y. J. Liu, Q. Kor, Katherine Hwee Boon Gan, C. L. |
| author_sort | Siah, Yu Wen |
| collection | NTU |
| description | Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization removal while reducing edge rounding on the sample during sample preparation that will preserve the integrity of the layers for further failure analysis. |
| first_indexed | 2024-10-01T03:20:11Z |
| format | Conference Paper |
| id | ntu-10356/143510 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:20:11Z |
| publishDate | 2020 |
| record_format | dspace |
| spelling | ntu-10356/1435102020-09-26T22:15:12Z Uniform delayering of copper metallization Siah, Yu Wen Hong, Y. J. Liu, Q. Kor, Katherine Hwee Boon Gan, C. L. School of Materials Science and Engineering 2013 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Temasek Laboratories Engineering::Materials Delayering Sample Preparation Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization removal while reducing edge rounding on the sample during sample preparation that will preserve the integrity of the layers for further failure analysis. Accepted version 2020-09-07T04:29:00Z 2020-09-07T04:29:00Z 2013 Conference Paper Siah, Y. W., Hong, Y. J., Liu, Q., Kor, K. H. B., & Gan, C. L. (2013). Uniform delayering of copper metallization. 2013 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 166-169. doi:10.1109/IPFA.2013.6599147 9781479912414 https://hdl.handle.net/10356/143510 10.1109/IPFA.2013.6599147 2-s2.0-84885673786 166 169 en © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, in any current or future media, including reprinting/republishing this material for adverstising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:https://doi.org/10.1109/IPFA.2013.6599147 application/pdf |
| spellingShingle | Engineering::Materials Delayering Sample Preparation Siah, Yu Wen Hong, Y. J. Liu, Q. Kor, Katherine Hwee Boon Gan, C. L. Uniform delayering of copper metallization |
| title | Uniform delayering of copper metallization |
| title_full | Uniform delayering of copper metallization |
| title_fullStr | Uniform delayering of copper metallization |
| title_full_unstemmed | Uniform delayering of copper metallization |
| title_short | Uniform delayering of copper metallization |
| title_sort | uniform delayering of copper metallization |
| topic | Engineering::Materials Delayering Sample Preparation |
| url | https://hdl.handle.net/10356/143510 |
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