Hardware efficient approximate adder design

Hardware efficient approximate adder design

This paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the...

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Bibliographic Details
Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas
Other Authors: School of Computer Science and Engineering
Format: Conference Paper
Language:English
Published: 2020
Subjects:
Engineering::Computer science and engineering::Hardware
Engineering::Electrical and electronic engineering::Integrated circuits
Approximate Computing
Computer Arithmetic
Online Access:https://hdl.handle.net/10356/143971

Internet

https://hdl.handle.net/10356/143971

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