A study of wireless inter-chip interconnect

In semiconductor industry, device feature dimension has been continuously scaled down to reduce device size and to improve circuit performance. In parallel with the device feature dimension down scaling, the width and thickness of wire interconnect have been reduced. On the other hand, to integrate...

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Bibliographic Details
Main Author: Chen, Zhiming
Other Authors: Zhang Yue Ping
Format: Thesis
Language:English
Published: 2008
Subjects:
Online Access:https://hdl.handle.net/10356/14559
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author Chen, Zhiming
author2 Zhang Yue Ping
author_facet Zhang Yue Ping
Chen, Zhiming
author_sort Chen, Zhiming
collection NTU
description In semiconductor industry, device feature dimension has been continuously scaled down to reduce device size and to improve circuit performance. In parallel with the device feature dimension down scaling, the width and thickness of wire interconnect have been reduced. On the other hand, to integrate more functions together, chip size continues growing. Therefore, the down-scaled wire interconnect has to route over an ever increasing chip area, implying degraded interconnect performance. As a matter of fact, performance of interconnects rather than device has become a bottleneck of ICs system performance. With improved radio frequency silicon technologies and higher-degree integration, wireless interconnect, which realizes wireless communications among cores within a chip or different chips within a module, is a viable candidate for solving problems in future generations of interconnects.
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spelling ntu-10356/145592023-07-04T17:00:29Z A study of wireless inter-chip interconnect Chen, Zhiming Zhang Yue Ping School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In semiconductor industry, device feature dimension has been continuously scaled down to reduce device size and to improve circuit performance. In parallel with the device feature dimension down scaling, the width and thickness of wire interconnect have been reduced. On the other hand, to integrate more functions together, chip size continues growing. Therefore, the down-scaled wire interconnect has to route over an ever increasing chip area, implying degraded interconnect performance. As a matter of fact, performance of interconnects rather than device has become a bottleneck of ICs system performance. With improved radio frequency silicon technologies and higher-degree integration, wireless interconnect, which realizes wireless communications among cores within a chip or different chips within a module, is a viable candidate for solving problems in future generations of interconnects. DOCTOR OF PHILOSOPHY (EEE) 2008-12-16T09:19:07Z 2008-12-16T09:19:07Z 2008 2008 Thesis Chen, Z. (2008). A study of wireless inter-chip interconnect. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/14559 10.32657/10356/14559 en 179 p. application/pdf
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Chen, Zhiming
A study of wireless inter-chip interconnect
title A study of wireless inter-chip interconnect
title_full A study of wireless inter-chip interconnect
title_fullStr A study of wireless inter-chip interconnect
title_full_unstemmed A study of wireless inter-chip interconnect
title_short A study of wireless inter-chip interconnect
title_sort study of wireless inter chip interconnect
topic DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
url https://hdl.handle.net/10356/14559
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