Towards designing a secure RISC-V system-on-chip : ITUS

Towards designing a secure RISC-V system-on-chip : ITUS

A rising tide of exploits, in the recent years, following a steady discovery of the many vulnerabilities pervasive in modern computing systems has led to a growing number of studies in designing systems-on-chip (SoCs) with security as a first-class consideration. Fol- lowing the momentum behind RISC...

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Bibliographic Details
Main Authors: Kumar, Vinay B. Y., Deb, Suman, Gupta, Naina, Bhasin, Shivam, Haj-Yahya, Jawad, Chattopadhyay, Anupam, Mendelson, Avi
Other Authors: School of Computer Science and Engineering
Format: Journal Article
Language:English
Published: 2021
Subjects:
Engineering::Computer science and engineering
Secure SoC
RISC-V
Online Access:https://hdl.handle.net/10356/147284

Internet

https://hdl.handle.net/10356/147284

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