A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS

A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS

Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-nm CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220...

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Bibliographic Details
Main Authors: Chacón, Oscar Morales, Wikner, Jacob, Alvandpour, Atila, Siek, Liter
Other Authors: School of Electrical and Electronic Engineering
Format: Conference Paper
Language:English
Published: 2021
Subjects:
Engineering::Electrical and electronic engineering
5G
Current-steering
Digital-to-Analog Converter
High Speed
CMOS
Radio Frequency
Low Power
Online Access:https://hdl.handle.net/10356/152100

Internet

https://hdl.handle.net/10356/152100

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