A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme

A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and...

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Bibliographic Details
Main Authors: Tang, Fang, Ma, Qiyun, Shu, Zhou, Zheng, Yuanjin, Bermak, Amine
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2022
Subjects:
Engineering::Electrical and electronic engineering
Successive Approximation Register
Analog-to-Digital Converter
Online Access:https://hdl.handle.net/10356/153966

Internet

https://hdl.handle.net/10356/153966

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