A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme
This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and...
| Main Authors: | , , , , |
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| Format: | Journal Article |
| Language: | English |
| Published: |
2022
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| Online Access: | https://hdl.handle.net/10356/153966 |
| _version_ | 1826126032764141568 |
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| author | Tang, Fang Ma, Qiyun Shu, Zhou Zheng, Yuanjin Bermak, Amine |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Tang, Fang Ma, Qiyun Shu, Zhou Zheng, Yuanjin Bermak, Amine |
| author_sort | Tang, Fang |
| collection | NTU |
| description | This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2 . At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step. |
| first_indexed | 2024-10-01T06:46:06Z |
| format | Journal Article |
| id | ntu-10356/153966 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:46:06Z |
| publishDate | 2022 |
| record_format | dspace |
| spelling | ntu-10356/1539662022-01-17T06:48:37Z A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme Tang, Fang Ma, Qiyun Shu, Zhou Zheng, Yuanjin Bermak, Amine School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering Successive Approximation Register Analog-to-Digital Converter This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2 . At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step. Published version This research was funded by the Natural Science Foundation of Chongqing, China grant cstc2019jcyj-zdxmX0014. 2022-01-17T06:48:37Z 2022-01-17T06:48:37Z 2021 Journal Article Tang, F., Ma, Q., Shu, Z., Zheng, Y. & Bermak, A. (2021). A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme. Electronics, 10(22), 2856-. https://dx.doi.org/10.3390/electronics10222856 2079-9292 https://hdl.handle.net/10356/153966 10.3390/electronics10222856 2-s2.0-85119286746 22 10 2856 en Electronics © 2021 The Author(s). Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering Successive Approximation Register Analog-to-Digital Converter Tang, Fang Ma, Qiyun Shu, Zhou Zheng, Yuanjin Bermak, Amine A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme |
| title | A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme |
| title_full | A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme |
| title_fullStr | A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme |
| title_full_unstemmed | A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme |
| title_short | A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme |
| title_sort | 28 nm cmos 10 bit 100 ms s asynchronous sar adc with low power switching procedure and timing protection scheme |
| topic | Engineering::Electrical and electronic engineering Successive Approximation Register Analog-to-Digital Converter |
| url | https://hdl.handle.net/10356/153966 |
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