Radiation hardened RISC-V processor
This thesis focuses on designing and validating an open-source 32-bit RISC-V processor and implementing using NTU’s in-house RHBD cell library. We inves tigate, analyse and compare the final layout in timing, area, and power based on three different libraries: (a) Full triple-module-redundancy (T...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/156208 |